搜索资源列表
DE2_Web_Server
- 此文件是altera公司发布的基于DE2开发板的-web例程，能实现DE2开发板与计算机之间的信息传输，采用vhdL语言编写。-This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.
hello
- VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。-VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fas
tutorial
- another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
Rapid_Prototyping_of_Digital_Systems__SOPC.tar
- Rapid prototyping of Digital system and SOPC VHDL Altera DE2 board
AnalizatorAndCounter
- VHDL counter project fo Altera DE2 Development Board-VHDL counter project fo Altera DE2 Development Board
digital-quadrature-down-converter
- 基于FPGA的数字正交下变频器设计,在ALTERA的DE2开发板上设计一个多相滤波结构数字正交变换器。其中多相滤波模块是最关键模块，该模块将64阶滤波器的系数分成奇偶两路，并通过VHDL常数的方式存储在模块内部。这些常数是通过在MATLAB中调用FDATool，根据滤波器的参数要求来生成的。这些浮点格式的滤波器系数还需要在MATLAB中计算成二进制补码的形式，才可以存储在模块中。-FPGA-based digital quadrature down-converter design, ALTER
I2C
- this vHDL code for I2C RTC i am usinf de2 board FPGA PLATFORM-this is vHDL code for I2C RTC i am usinf de2 board FPGA PLATFORM
frequency_VHDL
- VHDL设计的频率计小系统，在ALtera的DE2板子上调试通过-VHDL design of the frequency meter small systems, the DE2 board in ALtera debugged
dianziqin
- VHDL语言编写的可以显示时钟的电子琴，使用Quatrus II开发，实验板为DE2-VHDL language keyboard that can display the clock, using Quatrus II development, test board for the DE2
jiaotongdeng
- 这是一个基于DE2开发板的用VHDL语言开发的模拟交通灯系统-This is based on the DE2 board' s language development using VHDL simulation traffic light system
TRABALHO4
- It s a sort of problem about sincronous operation using vhdl em DE2. Another homework lesson.
Locking_device
- EDA课程设计，基于DE2板的八位十进制锁码器，vhdl源程序！-EDA curriculum design, based on the DE2 board to eight decimal lock code reader, vhdl source code!
part1
- Altera DE2 开发板试验2 第1部分VHDL答案-Altera DE2 Lab2 part1 VHDL answer
part2
- Altera DE2 开发板试验2 第2部分VHDL答案-Altera DE2 Lab2 part2 VHDL answer
part3
- Altera DE2 开发板试验2 第3部分VHDL答案-Altera DE2 Lab2 part3 VHDL answer
part4
- Altera DE2 开发板试验2 第4部分VHDL答案-Altera DE2 Lab2 part4 VHDL answer
part5
- Altera DE2 开发板试验2 第5部分VHDL答案-Altera DE2 Lab2 part5 VHDL Answer
pptest
- vhdl代码的乒乓球游戏程序，使用de2平台验证-vhdl code of the table tennis games, platform verification using de2
inverse_counter
- 利用ALTERA的DE2实现4位可逆计数器，并进行7段译码显示，VHDL编写-4-bit counter with 7-segment display using VHDL